1. Field of the Invention
The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to integrated circuit memory devices having clocked access cycles and methods of operation thereof.
2. Statement of the Problem
Integrated circuit memory devices are used to store information in a wide variety of electronic devices including, among others, personal computers, personal digital assistants, cellular radiotelephones and the like. For example, an integrated circuit memory device may be used to store data for retrieval and processing by a microprocessor or similar data processing device. To read data stored in a memory cell of a memory device, the microprocessor typically supplies an address to an address input of the integrated circuit device, e.g., drives an address bus to which the microprocessor and the memory device are connected, the signals applied to the address bus corresponding to the desired memory cell. In response, the memory device produces the data stored in the desired cell at an output port, e.g., drives a data bus connecting the memory and the microprocessor with signals corresponding to the data stored in the desired memory cell. As the design of microprocessor systems has advanced, the demands on memory devices have increased. In particular, higher processor speeds have led to demands for increased data throughput between memory devices and processors.
Many integrated circuit memory devices operate according to a clocked memory access cycle. For example, ferroelectric random access memory (FeRAM) devices typically operate according to an access cycle that is controlled by a memory clock signal which may be externally supplied or internally generated. After an externally supplied address is used to generate internal row and column addresses, the state of a ferroelectric memory element, e.g., a ferroelectric capacitor, is sensed, typically by measuring charge transfer from the ferroelectric element. The sensing operation may be destructive, e.g., the charge transfer may result in a change of the polarization state of the ferroelectric capacitor. Accordingly, the access cycle often includes a restore cycle in which the original polarization of the ferroelectric capacitor is restored. Synchronous memory devices, such as synchronous dynamic random access memory (SDRAM) devices and synchronous static random access memory (SSRAM) devices, may also use a clocked access cycle controlled by a memory clock signal.
In many nonvolatile and static memory applications, however, synchronous operation between a memory device and external devices may not be desirable. In such applications, a read cycle may be initiated simply by asserting a Chip Enable (CE) signal and applying an address signal to a memory device's address input to access the addressed memory cell. In response, a signal corresponding to the contents of the addressed memory cell is asserted at an output port of the memory device within tens of nanoseconds of the address assertion. A new memory cell can be accessed by holding the signal constant and asserting a new address at the address input in a generally asynchronous manner.
Accordingly, in many memory applications it is desirable to access a memory device in an asynchronous manner, i.e., without requiring dependence on a common clock signal. Unfortunately, many memory devices that may be well suited for static memory applications, such as ferroelectric memory devices, are more desirably operated according to a clocked access cycle.